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Description: xlinukx 中文教程，对FPGA新手及英文不好的朋友很有用-xlinukx Chinese guides, the FPGA novice English is not good and very useful friends
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Size: 277504 |
Author: 张弛 |
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Description: FPGA/CPLD集成开发环境ise的使用详解 示例代码9-FPGA/CPLD Integrated Development Environment ise Comments on the use of code examples 9
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Size: 5120 |
Author: bigbibby |
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Description: XILINX开发环境ISE的入门操作指导，对于FPGA的初学者有较大的帮助。-XILINX ISE development environment operating guidance for beginners, For FPGA beginners have more help.
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Size: 286720 |
Author: liujie |
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Description: 本代码介绍了使用VHDL开发FPGA的一般流程，最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL，在软件开发平台ISE上完成，可以在较高速时钟频率（100MHz）下正常工作。该设计的频率计能准确的测量频率在1Hz到100MHz之间的信号。使用ModelSim仿真软件对VHDL程序做了仿真，并完成了综合布局布线，最终下载到芯片Spartan-II上取得良好测试效果。-the code on the FPGA using VHDL development of the general process, finally adopted a FPGA-based digital frequency method. The design using VHDL hardware description language, the software development platform ISE completed, the higher speed clock frequency (100MHz) under normal work. The design of the frequency meter can be accurately measured in a frequency of 100MHz between Hz signal. Use ModelSim VHDL simulation software to do the simulation process, and completed a comprehensive layout cabling, downloaded to the final chip Spartan-II made good on the test results.
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Size: 515072 |
Author: 许的开 |
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Description: 用中文介绍Xilinx公司FPGA/CPLD的集成开发环境－ISE软件的简单使用
-Introduction to Chinese Xilinx Inc. FPGA/CPLD integrated development environment-ISE software simple to use
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Size: 825344 |
Author: Kuben |
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Description: ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）
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Size: 1022976 |
Author: yuling |
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Description: 华为FPGA设计流程指南，FPGA设计者、项目管理者必读的文档，看看别人是怎么做的。-Huawei FPGA design flow guide, FPGA designers, project managers must-read documents, take a look at how others do.
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Size: 31744 |
Author: 贺雷 |
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Description: 本文：采用了FPGA方法来模拟高动态(Global Position System GPS)信号源中的C／A码产生器。C／A码在GPS中实现分址、卫星信号粗捕和精码(P码)引导捕获起着重要的作用，通过硬件描述语言VERILOG在ISE中实现电路生成，采用MODELSIM、SYNPLIFY工具分别进行仿真和综合。-This article: FPGA method used to simulate the high dynamic (Global Position System GPS) signal source of the C/A code generator. C/A code in GPS to achieve sub-sites, the satellite signal capture coarse and fine code (P code) lead capture plays an important role, through hardware description language Verilog in ISE to achieve circuit to generate, using MODELSIM, SYNPLIFY simulation tools were and integrated.
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Size: 163840 |
Author: xiaozhu |
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Description: 本系统使用VHDL语言进行设计，采用自上向下的设计方法。目标器件选用Xilinx公司的FPGA器件，并利用Xilinx ISE 7.1 进行VHDL程序的编译与综合，然后用Modelsim Xilinx Edition 6.1进行功能仿真和时序仿真。-The system design using VHDL language, using top-down design method. Selection of the target device Xilinx
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Size: 297984 |
Author: 西西 |
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Description: 开发环境是QUARTUSI,ISE等FPGA开发工具，本问主要描述FGPA开发过程中需要注意的时序-Development environment is QUARTUSI, ISE and other FPGA development tools, the principal asked to describe the process of developing FGPA need to pay attention to timing
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Size: 1510400 |
Author: horse |
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Description: xilinx ise 7.1下 实现sparten3 basys板上基于8086FPGA软核的吃豆子游戏-xilinx ise 7.1 under sparten3 basys board based on soft-core 8086FPGA eating beans games
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Size: 2360320 |
Author: 朱万里 |
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Description: 图像处理，实现一个显示器接口，实现了编码和解码
使用方法：
1.拷贝到硬盘，用ISE打开工程文件即可。
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Size: 129024 |
Author: xiexiao |
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Description: 一个基于FPGA的游戏,其中包含多个项目,有吃豆子,可以连接到LCD的显示输出.该源码用xilinx的ise仿真综合成功,并且用spartan3开发板测试.可以有2个人在键盘上对弈.
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Size: 2048 |
Author: 陈想 |
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Description: ISE最常用的FPGA、CPLD开发软件教程，对代码的编绎、下载等环节十分有用。-ISE the most commonly used FPGA, CPLD development software tutorials, code editing and Sounds, download links, such as very useful.
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Size: 277504 |
Author: QGP |
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Description: 用FPGA实现数字锁相环，开发环境为ISE-Using FPGA digital phase-locked loop, development environment for ISE
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Size: 178176 |
Author: 冯勇 |
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Description: 本文介绍了一个使用 VHDL 描述计数器的设计、综合、仿真的全过程，作为我这一段
时间自学 FPGA/CPLD 的总结，如果有什么不正确的地方，敬请各位不幸看到这篇文章的
大侠们指正，在此表示感谢。当然，这是一个非常简单的时序逻辑电路实例，主要是详细
描述了一些软件的使用方法。文章中涉及的软件有Synplicity 公司出品的Synplify Pro 7.7.1；
Altera 公司出品的 Quartus II 4.2；Mentor Graphics 公司出品的 ModelSim SE 6.0。 -This article describes a VHDL description of the use of counter design, synthesis, simulation of the entire process, this time as my self-FPGA/CPLD summary, if what has not the right place, please see this article that, unfortunately, the heroes They correct me, wish to express my gratitude. Of course, this is a very simple example of sequential logic circuit is mainly a detailed description of a number of software usage. Article involved in the software company has produced Synplicity
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Size: 1945600 |
Author: 黄鹏曾 |
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Description: Xilinx ISE中文简明教程、Xilinx术语中文.pdf、Virtex 系列 FPGA 的配置和回读、FPGA设计检查清单.pdf、设计注意.pdf、逻辑设计注意列表.pdf-Xilinx ISE Chinese Concise Guide, Xilinx Chinese terminology. Pdf, Virtex Series FPGA configuration and read-back, FPGA design checklist. Pdf, design attention. Pdf, logic design attention to the list. Pdf
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Size: 1970176 |
Author: veraking |
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Description: 本章详细介绍了基于ISE的FPGA设计流程以及多个辅助工具（XST、XPower、PACE、ModelSim、Synplify以及MATLAB）的使用方法。首先介绍了ISE软件主要特性及其安装流程，然后介绍了如何通过ISE完成FPGA设计，-This chapter details the FPGA-based ISE design flow, as well as a number of auxiliary tools (XST, XPower, PACE, ModelSim, Synplify, and MATLAB) to use. First introduced the main features of ISE software and its installation process, and then describes how the adoption of ISE complete FPGA design,
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Size: 7639040 |
Author: 马军辉 |
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Description:
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Size: 333824 |
Author: bluefeifei |
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Description: 一个完全好用的程序,用ISE 8.2打开就可直接应用-A fully-to-use procedures, with ISE 8.2 can be applied directly to open
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Size: 620544 |
Author: Ma liang |
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